High speed configuration independent programmable macrocell

ABSTRACT

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

This is a continuation of application Ser. No. 08/360,469, filed Dec.20, 1994, now U.S. Pat. No. 5,502,403.

FIELD OF THE INVENTION

The present invention relates to the field of programmable logicdevices, and more particularly to a high speed programmable macro cellwith a propagation delay independent of the configuration.

BACKGROUND OF THE INVENTION

In general, programmable logic devices (PLDs) permit a user to configurethe PLD device to accommodate a wide spectrum of applications. One typeof PLDs has a programmable macro cell. The programmable macro cellprovides the capability of defining the architecture of each outputindividually. Each of the potential outputs may be specified to be“registered” or “combinatorial”. In addition, the polarity of eachoutput may also be individually selected allowing complete flexibilityof the output configuration. In addition, further configurability isprovided through “array” configurable “output enable” for each potentialoutput. This feature allows the outputs to be reconfigured as inputs onan individual basis, or alternatively, used as a combinational I/Ocontrolled by the programmable array. An example of such a PLD device ismanufactured by Cypress Semiconductor Corporation, the Assignee of thepresent invention.

FIG. 1 illustrates a user configurable macro cell configured inaccordance with the prior art. For the circuit illustrated in FIG. 1,the user selects the configuration of the macro cell to operate aseither a D-type flip-flop or a T-type flip-flop. In addition, the userselects the polarity of the output data (e.g. whether the output of thecircuit is selected from the register true (Q) or bar ({overscore(Q)})). Typically, the user selects the configuration by programminguser configurable bits. In response to the user configurable bits, aD-type, a T-type, a polarity, {overscore (Dtype)}, a {overscore (Ttype)}and {overscore (polarity)} select signals are generated. A macrocell 100receives the D-type, T-type, polarity, {overscore (Dtype)}, {overscore(Ttype)} and {overscore (polarity)} select signals.

The macro cell circuit 100 contains an exclusive OR gate (XOR) 102, aregister 120, and a plurality of transmission gates 105, 110, 152 and154. The XOR gate 102 implements the toggle function for the T-typeflip-flop. As is shown in FIG. 1, transmission gates 105, 110, 115, 125,140, 148, 154 and 152 contain a p channel metal oxide semiconductor(MOS) transistor and an n channel MOS transistor. The register 120, usedto implement the D-type and the T-type flip-flops, contains a masterlatch, a slave latch and a transmission gate 140 used to couple themaster latch and the slave latch. The master latch includes inverters130 and 135, as well as transmission gate 125. The slave latch includesinverters 145 and 146, as well as transmission gate 148.

The “Data In” is input to the XOR 102 and a transmission gate 105. If aD-type flip-flop is specified by the static control signals, then thetransmission gate 105 conducts the “data in” signal to a transmissiongate 115. If the static control signals specify a T-type flip-flop, thenthe output of the XOR gate 102 is coupled to the transmission gate 115via the transmission gate 110.

During a clock transition from a high state to low logic state, the datainput to transmission gate 115 is passed to the master latch. Also,during the high state to low logic state transition, the transmissiongates 125 and 140 are closed disabled, and the transmission gate 148 isopen enabled to latch or retain the state previously latched in theslave latch. When the clock cycle transitions to a high logic level, thetransmission gate 140 and the transmission gate 125 are opened enabledto latch the data in the master latch, and to pass the data into theslave latch, inverters 145 and 146. In addition, in the high clockcycle, the transmission gate 148 is closed disabled. The polarity and{overscore (polarity)} static signals select either the true or baroutputs of the register 120 to generate the “data out”.

Although the macro cell circuit 100 provides selectable D-type or T-typeconfigurations, the T-type configuration requires a longer set-up timethan the D-type configuration due to the XOR gate 102. In addition, thedata path for the D-type configuration includes transmission gate 105,and the data path for the T-type configuration includes transmissiongate 110. Furthermore, whether the T-type or D-type configurations areselected, the data is further delayed by the transmission gates 152 and154 utilized to select the polarity.

SUMMARY AND OBJECTS OF THE INVENTION

Therefore, it is an object of the present invention to reduce thepropagation delay of the data path in a user configurable circuit.

It is another object of the present invention to provide a high speeduser configurable circuit, wherein the propagation delays areindependent of the configuration.

These and other objects are included in a circuit that contains clocklogic, a switching element and a data path circuit. Input data isreceived in the switching element, and the switching element and thedata path circuit constitute the entire data path for the circuit. Aplurality of user configurable inputs are received to configure thecircuit for a particular user application. The clock logic and theswitching element implement a logic function that is configurable by theuser configurable inputs. The logic function is pre-processed in theclock logic so that minimal delay occurs in the data path. In addition,the propagation delay through the switching element and the data pathcircuit is independent of the user configurable inputs.

The clock logic receives the user configurable inputs and a clock input.In turn, the clock logic generates conditional clock signals toimplement the logic function for the circuit based on the clock inputand the user configurable inputs. The switching element includes atleast one transmission gate that is controlled by the conditional clocksignals. The transmission gate includes any type of pass gate, such as athree state inverter or a switching transistor. The switching elementgenerates a logic output, in accordance with the conditional clocksignals, to implement the logic function by controlling propagation ofthe input signal through the transmission gate. The data path circuitreceives the logic output, and is also controlled by the conditionalclock signals.

The circuit of the present invention has application for use as a macrocell for a programmable logic device. In one embodiment, the data pathcircuit is a storage element, and the user configurable inputs include aD-type register select, a T-type resister select, a latch select, and apolarity select. The logic functions implemented in the clock logic area multiplexer function, for selecting among a D-type flip-flop, a T-typeflip-flop and a latch, and a polarity function for generating a true ora bar output for the circuit. The storage element is configured as amaster/slave flip-flop, and includes a master latch, that receives thelogic output, and a slave latch that couples the master latch to thecircuit output.

Other objects, features and advantages of the present invention will beapparent from the accompanying drawings, and from the detaileddescription that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features, and advantages of the present invention will beapparent from the following detailed description of the preferredembodiment of the invention with references to the following drawings.

FIG. 1 illustrates a user configurable macro cell configured inaccordance with the prior art.

FIG. 2 is a high level block diagram illustrating the user configurablecircuit of the present invention.

FIG. 3 is a block diagram illustrating a user configurable circuitconfigured in accordance with the present invention.

FIG. 4 illustrates one embodiment for implementing the user configurablecircuit 300 illustrated in FIG. 3.

FIG. 5 illustrates a programmable macro cell incorporating the userconfigurable circuit of the present invention.

DETAILED DESCRIPTION

FIG. 2 is a high level block diagram illustrating the user configurablecircuit of the present invention. A user configurable circuit 200receives, as inputs, a plurality of user configurable inputs. Forpurposes of explanation, the user configurable circuit 200 receives“0−n” user configurable inputs. The user configurable circuit 200contains clock logic 210, a switching element 205, and a data pathcircuit 215. The user configurable circuit 200 also receives a clocksignal, at the “clock in” terminal, that provides timing for thecircuit. Although the present invention is described in conjunction witha clock signal, any dynamic control signal used to gate input data maybe used without deviating from the spirit and scope of the invention.Data is input to the switching element 205 at the “data in” terminal.

The clock logic 210 receives both the plurality of user configurableinputs, and the clock. In a preferred embodiment, the user configurableinputs are set or programmed by the user in an initialization period.Specifically, the user configurable inputs are programmed into anon-volatile memory, thereby storing user configurable bits in a PLDapplication. In the preferred embodiment, the user configurable bits arestored in an electrically erasable programmable read only memory(EEPROM). In an alternative embodiment, the user configurable inputs maybe stored in a register, such as a serial shift register or a staticrandom access memory (SRAM). After the initialization period, and uponpowering of the user configurable circuit 200, the user configurableinputs do not change state, and therefore are characterized as pseudo DCsignals. The circuitry utilized to set the user configurable inputduring the initialization period is well known in the art and will notbe described further. The clock logic 210 generates a conditional clocksignals205 , labeled as conditional clock signals 0−m on FIG. 2.

The switching element 205 receives the conditional clock signals “0−m”and the data input. In general, the clock logic 210 and the switchingelement 205 implement at least one logic function for the userconfigurable circuit 200. For example, the clock logic 210 and theswitching element 205 may implement a multiplexing function to selectamong three configurations such as a D-Type flip flop, T-type flip-flopand latch. The output of the switching element 205 is, coupled to theinput of data path circuit 215. The data path circuit 215 may compriseany type of circuit, such as a registered or combinational, used toimplement the user configurable circuit. One embodiment for the datapath circuit 215 is described more fully below. The output of data pathcircuit 215 is labeled “data output” on FIG. 2. The output of data pathcircuit 215 is also coupled to the clock logic 210 to provideimplementation of certain flip flop functions.

In one embodiment, the switching element 205 gates the data input withthe clock to provide synchronous operation between the input data andthe data path circuit 215. In a preferred embodiment, the switchingelement 205 contains at least one gating or pass gate element, such as atransmission gate. However, the transmission gate may include any typeof pass gate, such as a three state inverter or a switching transistor,without deviating from the spirit or scope of the invention. Oneembodiment for gating the input data in the switching element 205 isdescribed more fully below. The conditional clock signals, generated inthe clock logic 210, are utilized to gate the input data in theswitching element 205.

The switching element 205 and the data path circuit 215 constitute thedata path for the user configurable circuit 200, and the clock logic 210provides the clock path for the user configurable circuit 200.Consequently, the critical path for reducing delay of the userconfigurable circuit 200 lies in the data path (e.g. data beingpropagated through the switching element 205 and data path circuit 215)and the clock path. In general, the user configurable circuit 200 isconstructed such that most of the processing to implement the logicfunction or logic functions are done prior to an active clock (e.g. inthe clock logic 210). Because the user configurable inputs are availableas pseudo DC signals after power-up, most of the processing for thelogic function occurs prior to receiving data for input to the datapath. Also, because the operation of the data path circuit 215 requiresgating the data, no additional delay is introduced to implement thelogic function or logic functions in the switching element 205. Becauseof the decrease in gates in the data path, propagation delay through theuser configurable circuit 200 is reduced.

FIG. 3 is a block diagram illustrating a user configurable circuitconfigured in accordance with the present invention. In general, a userconfigurable circuit 300 permits a user to select among configuring thecircuit as a D-type flip-flop, a T-type flip-flop or a latch. Inaddition, the user configurable circuit 300 permits a user to select thepolarity of the data output. The user configurable circuit 300 containsclock logic 310, D-type flip-flop/T-type flip-flop/latch logic (D/T/L)element 320 and a register 330. The clock logic 310 receives functionselect and polarity select signals as user configurable inputs. In turn,the clock logic 310 generates conditional clock signals for the D/T/Lelement 320 and the register 330.

In general, the clock logic 310 and the D/T/L element 320 executes thetoggle function, the polarity function, and a multiplexing function toselect among the T-type flip-flop, the D-type flip-flop or latchconfiguration. The data input is received in the D/T/L element 320. TheD/T/L element 320 is coupled to the register 330, and the data areoutput from the register 330. The data output are also input to theclock logic 310 in order to implement the T-type flip-flop function.

During a configuration period for the user configurable circuit 300, thefunction select and the polarity select signals are set. After the userconfigurable circuit 300 is powered up, the clock logic 310 generatesthe conditional clock signals in accordance with the function select andpolarity select signals and the clock signal. During the rising edge ofthe clock, the data input are gated in the D/T/L element 320 inaccordance with the conditional clock signals. The propagation delay inthe D/T/L element 320 is equal to the propagation delay from onetransmission gate. During the falling edge of the clock, data arelatched in the register 330. The control of the data through theregister 330 is also conducted by the conditional clock signals.

FIG. 4 illustrates one embodiment for implementing the user configurablecircuit 300 illustrated in FIG. 3. A user configurable circuit 400implements the D/T/L element 320 with a D/T/L element 420, the clocklogic 310 with clock logic 410, and the register 330 with register 430.The D/T/L element 420 contains a three state inverter 335 and atransmission gate 332. The three state inverter 335 includes a CMOSinverter comprising p channel transistor 336 and n channel transistor338. The three state inverter 335 further includes p channel transistor334 coupled between the source of p channel transistor 336 and Vcc, andan n channel transistor 340 coupled between the source of n channeltransistor 338 and ground. The register 430 contains a master latch 345and a slave latch 355. The master latch 345 includes inverters 344 and346, and a transmission gate 342. The slave latch 355 comprisesinverters 352 and 354, and a transmission gate 350. The register 330further includes a transmission gate 348 coupling the master latch withthe slave latch.

As discussed above in conjunction with FIG. 3, the user configurableinput defines the function selected, either the D-type flip-flop, T-typeflip-flop or latch, and the polarity output from the circuit. As shownin FIG. 4, the clock logic 410 receives user configurable bits C2, C3,and C4. As discussed above, the user configurable bits C2, C3, and C4are programmed during an initialization period, and are stored innon-volatile memory or registers. The clock logic 410 also receives theclock input. The clock logic 410 generates clock 1 (CLK 1), clock 1 bar({overscore (CLK1+L )}), clock 2 (CLK 2), clock 2 bar ({overscore(CLK2+L )}), clock 3 (CLK 3), clock 3 bar ({overscore (CLK3+L )}), clock4 (CLK 4), clock 4 bar ({overscore (CLK4+L )}), clock 5 (CLK 5), andclock 5 bar ({overscore (CLK5+L )}) signals.

The CLK 1 and {overscore (CLK1+L )} signals control the enabling of thethree state inverter 335, and the CLK 2 and {overscore (CLK2+L )}signals control the transmission gate 332. The {overscore (CLK3+L )}signal controls the p channel transistors in transmission gates 342 and348, and the CLK 3 signal controls the n channel transistors intransmission gates 342 and 348. The {overscore (CLK4+L )} signalcontrols the p channel transistor in transmission gate 358, and the CLK4 signal controls the n channel transistor in transmission gate 358. Inaddition, the {overscore (CLK5+L )} signal controls the n p channeltransistor in transmission gate 350, and the CLK 5 signal controls the pn channel transistor in transmission gate 350.

In operation, data are input to the D/T/L element 420 on the {overscore(Data In)} line. If the configurable circuit 300 is operating in theD-type flip-flop mode, and the polarity select indicates a bar output,then the CLK 1 and {overscore (CLK1+L )} signals disable the three stateinverter 335, and the CLK 2 and {overscore (CLK2+L )} signals togglesthe transmission gate 332. For the embodiment illustrated in FIG. 4, thebar output is Data Out. If the function select indicates a D-typeflip-flop and the polarity select indicates a true output, then the CLK1 and {overscore (CLK1+L )} signals toggles the three state inverter 335to pass data from the {overscore (Data In)} to the output of the D/T/Lelement 420, and the CLK 2 and {overscore (CLK2+L )} signals disable thetransmission gate 332. Therefore, the D-type select and the polarityfunctions are primary implemented in the clock logic 310. Consequently,only one gate delay occurs in the D/T/L element 420 (e.g. either throughthe three state inverter 335 or the transmission gate 332).

As shown in FIG. 4, the output of the register 430 is coupled to theclock logic 410 to implement the T-type flip-flop function. In theT-type mode, the data output is toggled when the {overscore (Data In)}is a low logic level, and the data output is not toggled when the{overscore (Data In)} is a high logic level. Consequently, knowledge ofthe current state stored in the slave latch 355 is required to implementthe T-type flip-flop function. If {overscore (Data In)} is “0”, and theslave latch 355 stores a “1”, and the T-type function select is active,then CLK 1 and {overscore (CLK1+L )} signals disable the three stateinverter 335, and the CLK 2 and {overscore (CLK2+L )} signals enable thetransmission gate 332 to pass a low logic level. If the T-type functionselect is active, Data In {overscore (Data In)} is “0”, and the slavelatch 355 stores a “0”, then the CLK 1 and {overscore (CLK1+L )} signalsenable the three state inverter 335, and the CLK 2 and {overscore(CLK2+L )} signals disable the transmission gate 332, thereby couplingthe output of three state inverter 335 to the register 430.

If the T-type select function is active, the {overscore (Data In)} is“1”, and the slave latch 355 stores a “0”, then the CLK 1 and {overscore(CLK1+L )} signals enable the three state inverter 335, and the CLK 2and {overscore (CLK2+L )} signals disable the transmission gate 332.However, if the T-type select is active, {overscore (Data In)} is “1”,and the slave latch 355 stores a “1”, then the CLK 1 and {overscore(CLK1+L )} signals disable the three state inverter 335, and the CLK 2and {overscore (CLK2+L )} signals enable the transmission gate 332.

When the user configurable circuit 400 is operating in the latch mode,the {overscore (Data In)} is passed directly to the register 430.Therefore, for operation in the latch mode with bar output, the CLK 1and {overscore (CLK1+L )} signals disable the three state inverter 335,and the CLK 2 and {overscore (CLK2+L )} signals enable the transmissiongate 332 independent of the clock signal. For latch mode with trueoutput, CLK2 and {overscore (CLK2+L )} disable transmission gate 332 andCLK1 and {overscore (CLK1+L )} signals enable three state inverter 335independent of clock signal. Regardless of the true or bar output, whenoperating in the latch mode, transmission gate 358 is enabled with theCLK 4 and {overscore (CLK4+L )} signals to bypass the master latch.

In the rising edge of the clock, data is passed from the {overscore(DataIn)} to the output of the D/T/L element 420 as described above, andthe data is latched in the master latch 345 when operating in both theT-type and D-type modes. When the user configurable circuit 400 isoperating in the latch mode, the CLK 4 and {overscore (CLK4+L )} signalsenable the transmission gate 358 to pass data from the output of theD/T/L element 420 to the slave latch 355. In all modes of operation, thedata is latched in the slave latch 355 and the data is output from themaster latch 345 during the falling edge of the clock.

For the user configurable circuit 400, the user configurable bits areC2, C3 and C4, and define the configuration of the circuit (e.g. togglemode, latch mode, and polarity select). Specifically, the userconfigurable bits C2, C3 and C4 define the operation of the userconfigurable circuit 400 as follows:

Treg=TOGGLE MODE={overscore (C3+L )}C2Treg=TOGGLE MODE={overscore(C3)}·C2

 C4=POLARITY ACTIVE HIGH

Latch=LATCH MODE=C3{overscore (C2+L )} Latch=LATCH MODE=C3·{overscore(C2)}

As shown in FIG. 4, the clock logic 410 generates the conditional clocksignals CLK 1, {overscore (CLK1+L )}, CLK 2, {overscore (CLK2+L )}, CLK3, {overscore (CLK3+L )}, CLK 4, {overscore (CLK4+L )}, CLK 5,{overscore (CLK5+L )}. The conditional clock signals are generated inthe clock logic 410 based on the following relationships:

CLK1=X{overscore (Clk)}+Latch C4CLK1=X·{overscore (Clk)}+Latch·C4

CLK2=Y{overscore (Clk)}+Latch {overscore (C4+L )} CLK2=Y·{overscore(Clk)}+Latch·{overscore (C4)}

CLK3=Clk{overscore (Latch)} CLK3=Clk·{overscore (Latch)}

CLK4=Clk Latch CLK4=Clk·Latch

CLK5={overscore (Clk)}

Where

Clk=CLOCK

Slave=FEEDBACK FROM THE SLAVE REGISTER 355

AND

X=Treg{overscore (Slave)}+{overscore (Treg)}C4X=Treg·{overscore(Slave)}+{overscore (Treg)}·C4

Y=SlaveTreg+{overscore (Treg C4+L )}Y=Slave·Treg+{overscore(Treg)}·{overscore (C4)}

The equations may be implemented using well known circuits. Table 1below provides a truth table corresponding to the equations above.

TABLE 1 Clock {overscore (Clk)} Cycle Slave C4 C3 C2 Clkb Clk1 Clk2 Clk3Clk4 Clk5  1 0 0 0 0 0 0 0 1 0 0  1 0 0 0 0 0 0 0 1 0 0  2 0 0 0 0 1 001 0 0 1  3 0 0 0 1 0 0 0 1 0 0  4 0 0 0 1 1 01 0 0 0 1  5 0 0 1 0 0 001 0 1 0  6 0 0 1 0 1 0 01 0 0 1  7 0 0 1 1 0 0 0 1 0 0  8 0 0 1 1 1 001 0 0 1  9 0 1 0 0 0 0 0 1 0 0 10 0 1 0 0 1 01 0 0 0 1 11 0 1 0 1 0 0 01 0 0 12 0 1 0 1 1 01 0 0 0 1 13 0 1 1 0 0 01 0 0 1 0 14 0 1 1 0 1 01 00 0 1 15 0 1 1 1 0 0 0 1 0 0 16 0 1 1 1 1 01 0 0 0 1 17 1 0 0 0 0 0 0 10 0 18 1 0 0 0 1 0 01 0 0 1 19 1 0 0 1 0 0 0 1 0 0 20 1 0 0 1 1 0 01 0 01 21 1 0 1 0 0 0 01 0 1 0 22 1 0 1 0 1 0 01 0 0 1 23 1 0 1 1 0 0 0 1 0 024 1 0 1 1 1 0 01 0 0 1 25 1 1 0 0 0 0 0 1 0 0 26 1 1 0 0 1 01 0 0 0 127 1 1 0 1 0 0 0 1 0 0 28 1 1 0 1 1 0 01 0 0 1 29 1 1 1 0 0 01 0 0 1 030 1 1 1 0 1 01 0 0 0 1 31 1 1 1 1 0 0 0 1 0 0 32 1 1 1 1 1 01 0 0 0 1

In a preferred embodiment, in addition to the logic shown in FIG. 4, theuser configurable circuit 300 contains set/reset logic. The operation ofset/reset logic to set the slave latch 355 as is well known in the art.In order to implement the polarity function through the clock logic 410,the set/reset logic is modified. When the polarity select is set totrue, and the set/reset logic is enabled, then the set/reset logic setsa high logic level in the slave latch 355. When the polarity select isset to a bar, and the set/reset logic is enabled, then a low logic levelis driven in the slave latch 355.

The present invention has application for use in a programmable macrocell. FIG. 5 illustrates a programmable macro cell incorporating theuser configurable circuit of the present invention. In general, aprogrammable macro cell 500 is configured in accordance with the userconfigurable circuit 200 shown in FIG. 2. The macro cell 500 may beconfigured as having combinatorial or registered outputs. In oneembodiment for the registered outputs, the programmable macro cell 500is configured in accordance with the user configurable circuit 400 topermit a user to select a T-type flip-flop, a D-type flip-flop, or alatch configuration. By using the user configurable circuit of thepresent invention as a programmable macro cell, the T-type flip-flop andthe D-type flip-flop configurations are specified as having equivalentpropagation delay times. In addition, the data path is reduced toprovide shorter propagation delays for both the T-type flip-flop and theD-type flip-flop configurations.

Although the present invention has been described in terms of specificexemplary embodiments, it will be appreciated that various modificationsand alterations might be made by those skilled in the art withoutdeparting from the spirit and scope of the invention as set forth in thefollowing claims.

What is claimed is:
 1. A circuit comprising: a plurality of userconfigurable inputs for configuring said circuit; clock logic coupled tosaid user configurable inputs and coupled to receive a clock input, saidclock logic for generating conditional clock signals to implement alogic function for said circuit based on said clock input and said userconfigurable inputs; a switching element including at least one passgate coupled to said clock logic to receive some of said conditionalclock signals and coupled to receive an input signal for said circuit,said switching element for generating a logic output, in accordance withsaid conditional clock signals, to implement said logic function bycontrolling propagation of said input signal through said pass gate; anda data path circuit coupled to receive said logic output and some ofsaid conditional clock signals for providing additional functionality,wherein propagation delay through said switching element to said datapath circuit is independent of said user configurable inputs.
 2. Thecircuit as set forth in claim 1, wherein said data path circuitcomprises a register.
 3. The circuit as set forth in claim 1, whereinsaid data path circuit comprises a combinatorial circuit.
 4. The circuitas set forth in claim 1, wherein said logic function implemented in saidclock logic comprises a multiplexer function.
 5. The circuit as setforth in claim 1, wherein said logic function implemented in said clocklogic comprises a decoder function.
 6. The circuit as set forth in claim4, wherein said multiplexer function comprises multiplexing between aD-type register, T-type register and a latch.
 7. The circuit as setforth in claim 1, wherein said logic function, implemented in said clocklogic, comprises a polarity function for generating a true or a baroutput for said circuit.
 8. The circuit as set forth in claim 1,wherein: said user configurable inputs comprise a D-type registerselect, a T-type resister select, a latch select and a polarity select;said logic function implemented in said clock logic comprises amultiplexer function, for selecting among a D-type flip-flop, a T-typeflip-flop and a latch, said logic function comprises a toggle functionfor implementing a T-type flip-flop, and said logic function comprises apolarity function for generating a true or a bar output for saidcircuit; and said data path circuit comprises a master latch, coupled toreceive said logic output, and a slave latch coupling said master latchand said circuit output.
 9. The circuit as set forth in claim 8, whereinsaid switching element comprises: a three state inverter coupled to saidinput signal and being controlled by said clock logic for inverting saidinput data in accordance with said D-type register select, said T-typeresister select, and said polarity select; and a transmission gatecoupled to said input signal and being controlled by said clock logicfor passing said input data in accordance with said D-type registerselect, said T-type resister select, and said polarity select.
 10. Aprogrammable logic device (PLD) comprising: a plurality of userconfigurable inputs for configuring said PLD; at least one macrocell,coupled to receive said user configurable inputs, said macrocellcomprising: clock logic coupled to said user configurable inputs andcoupled to receive a clock input, said clock logic for generatingconditional clock signals to implement a logic function for said circuitbased on said clock input and said user configurable inputs; a switchingelement including at least one transmission gate coupled to said clocklogic to receive some of said conditional clock signals and coupled toreceive an input signal for said circuit, said switching element forgenerating a logic output, in accordance with said conditional clocksignals, to implement said logic function by controlling propagation ofsaid input signal through said transmission gate; and a data pathcircuit coupled to receive said logic output and some of saidconditional clock signals for providing additional functionality,wherein propagation delay through said switching element to said datapath circuit is independent of said user configurable inputs.
 11. Theprogrammable logic device as set forth in claim 10, wherein said datapath circuit comprises a register.
 12. The programmable logic device asset forth in claim 10, wherein said data path circuit comprises acombinatorial circuit.
 13. The programmable logic device as set forth inclaim 10, wherein said logic function implemented in said clock logiccomprises a multiplexer function.
 14. The programmable logic device asset forth in claim 10, wherein said logic function implemented in saidclock logic comprises a decoder function.
 15. The programmable logicdevice as set forth in claim 11, wherein said multiplexer functioncomprises multiplexing between a D-type register, T-type register and alatch.
 16. The programmable logic device as set forth in claim 10,wherein said logic function, implemented in said clock logic, comprisesa polarity function for generating a true or a bar output for saidcircuit.
 17. The programmable logic device as set forth in claim 10,wherein: said user configurable inputs comprise a D-type registerselect, a T-type resister select, a latch select and a polarity select;said logic function implemented in said clock logic comprises amultiplexer function, for selecting among a D-type flip-flop, a T-typeflip-flop and a latch, said logic function comprises a toggle functionfor implementing a T-type flip-flop, and said logic function comprises apolarity function for generating a true or a bar output for saidcircuit; and said data path circuit comprises a master latch, coupled toreceive said logic output, and a slave latch coupling said master latchand said circuit output.
 18. The programmable logic device as set forthin claim 17, wherein said switching element comprises: a three stateinverter coupled to said input signal and being controlled by said clocklogic for inverting said input data in accordance with said D-typeregister select, said T-type resister select, and said polarity select;and a transmission gate coupled to said input signal and beingcontrolled by said clock logic for passing said input data in accordancewith said D-type register select, said T-type resister select, and saidpolarity select.
 19. A method for configuring a circuit comprising thesteps of: receiving a plurality of user configurable inputs forconfiguring said circuit; receiving a clock input; generatingconditional clock signals to implement a logic function for said circuitbased on said clock input and said user configurable inputs; receivingan input signal for said circuit in a switching element including atleast one pass gate; receiving some of said conditional clock signals insaid switching element; generating a logic output from said switchingelement, in accordance with said conditional clock signals, to implementsaid logic function by controlling propagation of said input signalthrough said transmission gate; and providing a data path circuitcoupled to receive said logic output and some of said conditional clocksignals for providing additional functionality, wherein propagationdelay through said switching element to said data path circuit isindependent of said user configurable inputs.
 20. A circuit comprising:a plurality of configurable inputs; clock logic generating a pluralityof conditional clock signals in response to a clock input and theconfigurable inputs, the conditional clock signals implementing a logicfunction; a pass gate controlling propagation of an input signal andgenerating a logic output in accordance with at least one of theconditional clock signals; and a data path circuit receiving (i) thelogic output of the pass gate and (ii) at least one of the remainingconditional clock signals, the data path circuit providing additionalfunctionality.
 21. The circuit of claim 20, wherein the data pathcircuit comprises a register.
 22. The circuit of claim 20, wherein thedata path circuit comprises a D-type flip-flop, a T-type flip-flop or alatch.
 23. The circuit of claim 22, further comprising set/reset logichaving an output coupled to an input of the D-type flip-flop, the T-typeflip-flop or the latch.
 24. The circuit of claim 20, wherein the datapath circuit comprises a D-type flip-flop.
 25. The circuit of claim 24,further comprising set/reset logic having an output coupled to an inputof the D-type flip-flop.
 26. The circuit of claim 20, wherein the datapath circuit comprises a combinatorial circuit.
 27. The circuit of claim20, wherein the data path circuit comprises a static random accessmemory cell.
 28. The circuit of claim 20, wherein the data path circuitcomprises a three state buffer.
 29. The circuit of claim 20, wherein thelogic function comprises a multiplexer function.
 30. The circuit ofclaim 20, wherein the logic function comprises a decoder function. 31.The circuit of claim 30, wherein the configurable inputs comprise bitsin a static random access memory.
 32. The circuit of claim 30, whereinthe configurable inputs comprise a polarity select bit.
 33. The circuitof claim 30, wherein the configurable inputs comprise one or morefunction select bits.
 34. The circuit of claim 20, wherein the logicfunction comprises a polarity function generating a true output and acomplementary output.
 35. The circuit of claim 20, wherein theconfigurable inputs comprise bits in a shift register, a static randomaccess memory or an electrically erasable and programmable read onlymemory.
 36. The circuit of claim 20, wherein the additionalfunctionality comprises a flip-flop function.
 37. The circuit of claim20, further comprising a feedback loop connecting an output of said datapath circuit to an input of said clock logic.
 38. A programmable logicdevice, comprising: a plurality of configurable inputs; clock logicgenerating a plurality of conditional clock signals in response to aclock input and the configurable inputs, the conditional clock signalsimplementing a logic function; a pass gate controlling propagation of aninput signal and generating a logic output in accordance with at leastone of the conditional clock signals; and a data path circuit receiving(i) the logic output of the pass gate and (ii) at least one of theremaining conditional clock signals, the data path circuit providingadditional functionality.
 39. The device of claim 38, wherein thepropagation is independent of the configurable inputs.
 40. A method forconfiguring a circuit, comprising the steps of: (a) generating a set ofconditional clock signals in response to a clock input and a pluralityof configurable inputs; (b) implementing a logic function at a switchcomprising at least one pass gate, said switch receiving an inputsignal; (c) generating a logic output from the switch in accordance withat least one of the conditional clock signals; and (d) controllingpropagation of the input signal through the switch in accordance with atleast one of the conditional clock signals.
 41. The method of claim 40,wherein the propagation is independent of the configurable inputs. 42.The method of claim 41, further comprising providing additionalfunctionality from a data path receiving (i) the logic output and (ii)at least one of the remaining conditional clock signals.